This invention relates to a semiconductor device comprising semiconductor chips stacked and, particularly, to a chip selection or designation technique.
Various techniques for chip selection or designation in multi-chip semiconductor device are known using a plurality of through-lines that are pierced through multiple chips. For example, known techniques are disclosed in U.S. Pat. No. 6,448,661 and U.S. 2003/0040131 A1 U.S. Pat. No. 6,649,428, which are incorporated herein by reference in their entireties.